Forum Discussion
paveetirrasrie_Altera
Frequent Contributor
7 months agoHello Mel_tong,
Good day to you.
Have you tried with design example instead? And the latency for A10 and Agilex 7 is different. This 2 board has different latencies.
Regards,
Pavee
mel_tong
New Contributor
7 months agoHi Pavee,
I used the example of E-Tile Ethernet IP for Intel Agilex 7 FPGA and it worked fine.
But I couldn't find design example of E-Tile Transceiver Native PHY Intel Agilex 7 FPGA IP, so I made one according to the User Guide. The result is unstable.
Can you provide an design example of E-Tile Transceiver Native PHY Intel Agilex 7 FPGA IP?And what is the latency of phy for Agilex 7? Do you have specific data?
Regards,
tong