Dynamic Reconfiguration Support For Our USB3 IP Core In Agilex-5

Hi Altera Team,

We are using Agilex 5, and in one of our projects we are implementing the Dynamic Reconfiguration IP. However, we are facing some issues.

We are using the GTS transceiver for our USB 3 Soft IP. In a standalone Gen1 design, we received a custom quartus.ini file from your team that enables the i_tx_pma_elecidle_sync and i_txclkdivrate_sync ports only when the clocking mode is configured to PMA clocking mode.It's working fine.However, with this configuration, we are unable to use the System PLL clocking mode.

In our project, we are implementing the Dynamic Reconfiguration IP to switch between Gen1 (SuperSpeed) and Gen2 (SuperSpeed Plus). As mentioned above, the Dynamic Reconfiguration IP only supports System PLL clocking mode and does not allow PMA clocking mode.

When we set the PMA configuration rule to Basic (or any other option), we are able to configure the transceiver in System PLL clocking mode. However, in this case, the two ports mentioned above are not generated, and these ports are required for USB 3 functionality.

We would like to have such quartus.ini file that supports System PLL clocking mode with i_tx_pma_elecidle_sync and i_txclkdivrate_sync ports.

Our Resources: Quartus Prime Pro 25.3 and Agilex-5 Premium development kit.

Could you please help us resolve this issue or suggest a supported configuration that meets these requirements?

Thank you for your support.