Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYour design is invalid as you haven't delimited the synthesizable part of your design from the non-synthesizable part (i.e. your testbench). You need to add DSP Builder Input and Output blocks around the synthesizable part.
Chapter 2 of http://www.altera.com/literature/hb/dspb/hb_dspb_std.pdf (http://www.altera.com/literature/hb/dspb/hb_dspb_std.pdf) should help.