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Altera_Forum's avatar
Altera_Forum
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17 years ago

DSP Builder to Modelsim II

Hi I have the following a HDL import of the following vhdl file to dsp builder simulink.

Hoewever I didn obtain correct output from the modelsim simulation or I would rather say that most of the outputs display '-' or 'X' and I have tons of following error:

There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

I followed several suggestion from the net but still to no success. Can anyone help me to take a look at my attached vhdl file and advise me on how to change my coding??

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi all, I realized where is the mistake. I didn not reset/declare the signal properly that caused the value undefined appear in the simulations