Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

DSP Builder to Modelsim II

Hi I have the following a HDL import of the following vhdl file to dsp builder simulink. Hoewever I didn obtain correct output from the modelsim simulation or I would rather say that most of th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi all, I realized where is the mistake. I didn not reset/declare the signal properly that caused the value undefined appear in the simulations