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Altera_Forum's avatar
Altera_Forum
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14 years ago

DSP builder Fatal Error

I tried to import an HDL in simulink, but an error message pops up and says "error generating simulation model" and the Matlab workspace shows the message: "DSP Builder Fatal Error: decision_1: Expected module port name identifier"

Could anyone tell me what that means? Thanks in advance...

P.S. This is my first experience with Quartus-VHDL-DSPBuilder, so my knowledge is very limited :)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Have you checked whether your VHDL file compiles with Quartus without using DSP Builder? If Quartus can't understand it, then neither can DSP Builder.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi dabuk,

    yes, compilation and synthesis are succesful in Quartus, actually also in simulation the design seems to be ok. The problem occur only when I try to import the project to Simulink.

    I thought that the problem was the number of input ports, so I reduced it, but the problem persists...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    What is 'decision_1'? is it the name of a port, or a particular block in the design?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi sharkster,

    'decision_1' is the name of the project I tried to import...