Honored ContributorI tried to import an HDL in simulink, but an error message pops up and says "error generating simulation model" and the Matlab workspace shows the message: "DSP Builder Fatal Error: decision_1: Expected module port name identifier"
Could anyone tell me what that means? Thanks in advance... P.S. This is my first experience with Quartus-VHDL-DSPBuilder, so my knowledge is very limited :)
Honored ContributorHave you checked whether your VHDL file compiles with Quartus without using DSP Builder? If Quartus can't understand it, then neither can DSP Builder.
Honored ContributorHi dabuk,
yes, compilation and synthesis are succesful in Quartus, actually also in simulation the design seems to be ok. The problem occur only when I try to import the project to Simulink. I thought that the problem was the number of input ports, so I reduced it, but the problem persists...Honored ContributorWhat is 'decision_1'? is it the name of a port, or a particular block in the design?
Honored ContributorHi sharkster,
'decision_1' is the name of the project I tried to import...
