Honored ContributorI see this in Stratix I datasheet but I can't find this mentioned anywhere on their site for Stratix II? Does Stratix II support it? Up to 200 MHz? :eek:
Honored ContributorStratix II wasn't created with any hooks for ZBT and Altera hasn't published any analysis on supporting this. It is probably safe to say that if someone wants to do ZBT, they will have to take this risk on themselves. ZBT isn't rocket science though so if you want to take some risk you should:
Pick an implementation strategy (pins to use, etc) Create a timing methodology Explore the datasheet for key parameters Perform a timing analysis This will get you most of the way there.Honored ContributorThanks. I think I can use a latency cycle between reads and writes in my system to work around the ZBT contention that would happen. Other option I was looking at was creating my own ZBT delay for the OE signal - perhaps with a 2x clock controlling the OE so the turn on time is delayed a bit.
Going with latency cycle for now since my system is reading 95% of the time. It won't hurt me much.Honored ContributorDid some analysis on this for a HCII device with the one bus turnaround solution. The results can be used for SII, SIIGX, etc. A write up and verilog ZBT SRAM controller design and testbench are attached. The ZBT SRAM bus models were used for timing simulation as well - they are removed from the zip file for licensing reasons.
