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Altera_Forum
Honored Contributor
18 years agoDid some analysis on this for a HCII device with the one bus turnaround solution. The results can be used for SII, SIIGX, etc. A write up and verilog ZBT SRAM controller design and testbench are attached. The ZBT SRAM bus models were used for timing simulation as well - they are removed from the zip file for licensing reasons.