Dear ZH-Intel,
Thank you for your response. To answer your questions:
1) unfortunately, the DPTX is embedded within a larger design I cannot share with you. We use dp tx core version v20.0.1, config without support for DP 1.4 and config without support for MST and without support for HDCP
2) The design is directly derived from the design example of the intel display port fpga ip core. We use the btc_xxx functions from the demo design, especially the function "btc_dptx_link_training"
3) Our setup is as you suggested: DPTX --> AUX analyzer --> monitor. I tested different types and length of cables including cables for 8K, but my design requires UHD only.
4) The link device contains a Xilinx IP core as far as I know. Are there any known incompabilities?
One interesting thing I noticed, is that during link training, the Xilinx core of the monitor requests 5 times the same settings for voltage and pre emphasis. At the 5th adjust request, the dptx core aborts. The intel core manual writes:
The source checks for the Link Driver setting adjust request (0x00206 – 0x00207) and responds accordingly.
In the same Link Driver setting, if the source has already repeated Training Pattern Sequence 2 for 5 times, the source will lower the Link Bandwidth (from HBR2 to HBR to RBR) in offset 0x00100, aborts Training Pattern Sequence 2, and restarts Link Training Pattern Sequence 1.
But the 5th request is never processed, the core aborts instantly. It may be the cause of some misunderstandig between the xilinx sink core and the Intel source core, whether 5 requests of the same values for voltage and preamp are allowed or if the 5th request is already a reason for abort(!). So the next voltage setting level 2 is never tested. We observed, that other sources (GPU) achieved link training results with this level 2 setting.
So one question is, if it is reasonable concerning the link training function to abort at the 5th request instead of processing the 5th request and abort at the 6th...
It would really help us a lot - I would say solve our problem - if we would have the source code of the function "btc_dptx_link_training". Since all other btc_ functions are already provided in the tx_syslib library, we that will be able to modify the link training process and hopefully achieve successfull training.
Please, can you provide us the source code of the function "btc_dptx_link_training" of the intel FPGA display port demo design?
Thank you in advance,
Stefan
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