New Contributor
New ContributorHi there,
Thank you for your answers. Concerning the remark 3 from user vgs above, our cables are of high quality and I tested several different ones. It rather seems to be a problem of the available patterns that are checked by the DPTX core.
I now have a second log with the same Intel FPGA DPTX core, but with a modified Xilinx DPRX design.
(please see the attached log, I had to zip it for upload reasons)
I short, the log contains the following:
* Try 5.4 Gbit/s up to voltage level 1 without reaching CR_DONE
* Try 2.7 Gbit/s up to voltage level 1, reach CR_DONE, try pre-amp to level 2, Intel DPTX core aborts
* Try 1.6 Gbit/s up to voltage level 1, reach CR_DONE, try pre-amp to level 2, Intel DPTX core aborts
Complete abort after about 110 ms.
So again, the Intel DPTX core aborts link training without trying voltage level 2. Reading the DP1.2 spec, I found in the description of address 0x0103: Bit 2 = MAX_SWING_REACHED
"The transmitter must support at least three levels of voltage swing, levels 0, 1 and 2. If only three levels of voltage swing are supported, then bit 2 must be set to 1 when bits 1:0 are set to 10b (level 2) and must be cleared in all other cases. ....."
During the test with speed 2.7 Gbit/s and 1.6 Gbit/s, MAX_SWING_REACHED is never set.
--> So why does the Intel DPTX core not test voltage level 2??
Thank you in advance!
Stefan
