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MLaks3's avatar
MLaks3
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6 years ago

DisplayPort IP evaluation

We have purchased Bitec's FMC-DP Version 11 and trying to evaluate DP IP on Cyclone 10GX Development Kit.

Quartus Version: Quartus Prime 19.3

Target Kit: Cyclone 10 GX FPGA Development Kit

We followed the steps described in Design Example User Guide to generate example design. Edited config.h and c10_dp_demo.v for taking Rev 11 changes. The generated sof/elf is not streaming any video. When the design was simulated, the test passes but the CRC_* values is always 0000. Simulation is stopping after frame 04, while the screen shot in User Guide shows simulation continuing till frame 0e.

Simulation Log:

# Testing Video Input Frame Number = 04

# SINK CRC_R = 0000, CRC_G = 0000, CRC_B = 0000,

# SOURCE CRC_R = 0000, CRC_G = 0000, CRC_B = 0000,

# Pass: Test Completed

Are there any pre-built SOF/ELF that we can try on Cyclone 10 GX Development Kit to rule out board issues? Any debugging tips for bringing up the example design.

5 Replies

    • MLaks3's avatar
      MLaks3
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      6 years ago

      Hi BCT_Intel,

      Thanks for the link. We tried the generated bit file and the file from master_image folder and the behavior is same.

      Our lab PC has a Nvidia Quadro P1000 Graphics card and I have set it to 1920x1080 resolution at 60Hz with True Color (32-bit) mode.

      After programming the bit file, no output was observed on the monitor. We tried observing the MSA attributes on Nios Terminal.

      Tx Channel attributes seems to be fine. Most of the TX MSA attributes are matching that of the reference design screen shot.

      As Tx subsystem is not receiving any video, TX Link configuration is 0.

      Rx Link configuration seems to be fine. It is detecting 4 lanes with link rate of 5.4Gbps.

      Rx MSA attributes are all 0. Maybe because of this, Rx subsystem is not able to send video stream to Tx subsystem. Attaching nios terminal log.

      Debug LED Status:

      D20 is always ON indicating that TX PLL is locked.

      D19 is always OFF indicating DP Sink is not generating output to DP Source subsystem.

      Can you please suggest how we can bring up the Rx Subsystem.

      • MLaks3's avatar
        MLaks3
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        6 years ago

        I have switched back to example design generated by Quartus 19.3 as it was more promising. I have set the graphics card to 1920x1080 resolution and the MSA attributes look much better, but still no video on the display.

        The RX MSA attributes, Link configuration and BER0 look good. Whenever my PC goes into stand-by mode, USER_LED[0] turns OFF and once the PC is ON, the LED glow again. The other USER_LEDs also exhibit correct behavior. This indicates that RX subsystem is working fine.

        In TX subsystem, MSA attributes look good but Lane Count and Link Rate are always 0. I will try debugging more on this issue. Any particular register settings that I should be looking at?

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi Sir,

    After you edit the config.h, do you rerun the build_sw.sh in script folder before recompile the design? and also regenerating the new .elf.

    On both MSA, can see the link is totally not up on TX side. Looks like there are some issue on the transceiver side. Maybe you have to debug it from a transceiver perspective.

    I found some collateral regarding transceiver. Not sure if this will helps. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an871.pdf