Forum Discussion
New ContributorDisplayPort IP evaluation
Frequent ContributorHi Sir,
You may use this design:
https://fpgacloud.intel.com/devstore/platform/18.0.0/Pro/intel-cyclone-10-gx-displayport-4kp60-with-video-and-image-processing-pipeline-retransmit-reference-design/
However, you will need to start it with QII 18.0 first. Once it work, only upgrade it to your target version.
New ContributorHi BCT_Intel,
Thanks for the link. We tried the generated bit file and the file from master_image folder and the behavior is same.
Our lab PC has a Nvidia Quadro P1000 Graphics card and I have set it to 1920x1080 resolution at 60Hz with True Color (32-bit) mode.
After programming the bit file, no output was observed on the monitor. We tried observing the MSA attributes on Nios Terminal.
Tx Channel attributes seems to be fine. Most of the TX MSA attributes are matching that of the reference design screen shot.
As Tx subsystem is not receiving any video, TX Link configuration is 0.
Rx Link configuration seems to be fine. It is detecting 4 lanes with link rate of 5.4Gbps.
Rx MSA attributes are all 0. Maybe because of this, Rx subsystem is not able to send video stream to Tx subsystem. Attaching nios terminal log.
Debug LED Status:
D20 is always ON indicating that TX PLL is locked.
D19 is always OFF indicating DP Sink is not generating output to DP Source subsystem.
Can you please suggest how we can bring up the Rx Subsystem.
- MLaks3
I have switched back to example design generated by Quartus 19.3 as it was more promising. I have set the graphics card to 1920x1080 resolution and the MSA attributes look much better, but still no video on the display.
The RX MSA attributes, Link configuration and BER0 look good. Whenever my PC goes into stand-by mode, USER_LED[0] turns OFF and once the PC is ON, the LED glow again. The other USER_LEDs also exhibit correct behavior. This indicates that RX subsystem is working fine.
In TX subsystem, MSA attributes look good but Lane Count and Link Rate are always 0. I will try debugging more on this issue. Any particular register settings that I should be looking at?
- MLaks3posted a file.
