Occasional ContributorDigit Reverse Order issue for INTEL FFT IP core
Hello Sir/Madam,
I am simulating the intel FFT IP core, and seems the index of non-natural order FFT output is not fully match the index digi reverse calculation.
Quartus prime pro 17.1
Modelsim-intel starter 10.5c
Windows 10 pro
Arria10gx
What I have done
1, create a Quartus project and install a Intel FFT IP core
2, Choose to generate the testbench when setting up the FFT IP core
3,start modelsm and compile vendor/user library using automatic generated msim_setup.tcl
4,use matlab2019b to generate IEEE754 format data source, 32bits single precision floating.
5,In testbench coding to load above data source into FFT input
6, simulation and observe FFT output
with above simulation flow ,I have done 2 simulation case, the difference is output order, one is natural order, another one is digit reverse. I will explain it one by one.
case 1
FFT configuration is as below
Length:256
Direction: forward
Data flow: variable streaming
Input order: Natural
Output order: Natural
Representation: single floating point
below is simulation , seems every signals are correct, and we can find 2 spike
at the output stream, one is at index 4, another one is at index 252.
because I use x = 10 * cos(2*pi*4*t) to generate data source in matlab2019b, so the above simulation result meet the my understanding, ie at 4hz(index 4) and symmetric location 252(index252) have 2 spike signals.
below is part of the m file used to generate signal source.
fs=256;N=256;
n=0:N-1;t=n/fs;
x = 10 * cos(2*pi*4*t);
y=fft(single(x),N);
mag=abs(y);
f=n*fs/N;
subplot(2,2,1),plot(x); %signal source
xlabel('time domain');
ylabel('Amptitude');title('Signal Source input N=256');grid on;
subplot(2,2,2),plot(f,mag);
xlabel('Frequency Domain/Hz');
ylabel('Amptitude');title('Direct FFT N=256');grid on;
realInput = real(x);
imagInput = imag(x);
realOutput = real(y);
imagOutput = imag(y);
realOutput_s =single(real(y));
imagOutput_s =single(imag(y));
for i = 1 : N
fprintf(f1,'%s\n',float2bin(single(realInput(i)))); % writing bin format sine_input_data_r.txt
fprintf(f1i,'%s\n',float2bin(single(imagInput(i)))); % writing bin format sine_input_data_i.txt
end
below is details about 2 location at index 4 and index 252
case 1 simulation meet my expectation.
case 2
the reason I test case 2 because when I was repeating input data source, need to keep a big IPG to avoid timing issue,you can check my SR https://community.intel.com/t5/FPGA-Intellectual-Property/Intel-FFT-IP-core-timing-issue/m-p/1190502#M21698 .
but that big IPG reduce the fft processing bandwidth, that is why I change to digit reverse to avoid timing issue, but seems I got another issue.
case2 FFT configuration is as below
Length:256
Direction: forward
Data flow: variable streaming
Input order: Natural
Output order: Digit reverse
Representation: single floating point
based on the understanding for digit reverse option, the output index should be digit reverse for natural 8 bit index .
because these 2 case have same data source, so we can expect same result with different output order .
for example
the spike at index 4(00000100) in case 1, in case 2 should be at index 32(00100000) , however I did find this spike ,but location is at 16(00010000) ,this is not match the address reverse calculation, this is my key question.
another spike at index 252(11111100) in case1, in case 2 should be at index 63(00111111) ,I did find this spike in case and location is matched.no issue for this one.
let's check the simulation as below
I attached my 2 projects here for further analysis ,so you can duplicate my issue.
1,unzip my project,you can put it into the d: , this is my original location
2,start modelsim
3, you might need edit the quartus path in msim_setup.tcl ,my quartus is located H:/intelfpga_pro/17.1/quartus/
4,goto D:\fftipsimulation\tfft\sim\mentor
source initial_setup.tcl
5,do run.do
6, if you need to control input data source only once
change multi_cycle=1'b0 in D:\fftipsimulation\tfft\sim\tfft_tb.v
7, you will see the issue I mentioned
thanks
Jim
