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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I need the output sample rate is 2.5 MHz. I build the system as two cascade decimation FIR filters, where the first one has the decimation factor of 12 and the following one has the decimation factor of 4. The filter seems to work. However, there is spurious signals in the spectrum of the output. This happens for some input frequencies, not all. I don't know what the problem is. Neither I know how to fix it. Any one has some suggestion?　Thank you very much in advance!

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The decimation polyphase structure consists of a delay line of length = taps.

    The taps are split into 48 groups e.g. if you have 48*3 taps(main filter) then polyphases are:

    p1 = 1:48:end

    p2 = 2:48:end

    ...etc

    p48 =48:48:end

    the multipliers are wired every 48 delay stages. Those in between are left as pipe only.

    The output is updated at the slow clock(2.5MHz) by accumulating the results of 48 polyphases. The coefficients take turns at the multiplier and you should use the correct order.

    It is in effect a TDM based structure since output is slower than input 48 times.

    There is plenty of literature around. I know altera got an example vhdl somewhere...