Decimatio FIR filter in FPGA

The decimation polyphase structure consists of a delay line of length = taps.

The taps are split into 48 groups e.g. if you have 48*3 taps(main filter) then polyphases are:

p1 = 1:48:end

p2 = 2:48:end

...etc

p48 =48:48:end

the multipliers are wired every 48 delay stages. Those in between are left as pipe only.

The output is updated at the slow clock(2.5MHz) by accumulating the results of 48 polyphases. The coefficients take turns at the multiplier and you should use the correct order.

It is in effect a TDM based structure since output is slower than input 48 times.

There is plenty of literature around. I know altera got an example vhdl somewhere...