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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thank you, kaz! The way that applies single rate filter by using FIR compiler and does decimation following works correctly. But using FIR compiler to implement decimation filter still doesn't work. I try to find relative errata about FIR compiler but find nothing.

That's great! The decimation polyphase structure could reduce resources. I'm not very clear about how to implement decimation filter in polyphase structure. Is that right to divide coefficients into several groups and apply them to the corresponding filters by using FIR compiler?