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Honored Contributor
Honored ContributorDecimatio FIR filter in FPGA
Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_ForumHonored Contributor
Honored ContributorYou can apply single rate filter then do decimation directly provided you cut off at the right frequency relative to your signal spectrum edge.
Additionally you can apply the same filter in a decimation polyphase structure. In your case you will have 48 polyphases and will need tap/48 multipliers only.
