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Altera_Forum
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16 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The problem seems that the FIR compiler implement downsampling before filtering. I use the same coefficients but let filters be single rate. Then I downsample the filter output by myself. I can get the right results. I'm wondering whether there is something wrong when I use FIR compiler to implement decimation filter.