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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It is best to model your case in Matlab e.g.(for -25MHz/26MHz):

x1 = exp(j*2*pi*(0:2^20-1)*-25/120); %complex sinusoid

x2 = exp(j*2*pi*(0:2^20-1)*26/120); %complex sinusoid

x = x1.*x2 %mixer

h = fir1(200,40/60); %or choose any other better cutoff as your filter

y = upfirdn(x,h,1,48) %apply filter/decimation

plot(20*log10(fftshift(abs(fft(y))))); %fft