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Honored Contributor
Honored ContributorDecimatio FIR filter in FPGA
Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_ForumHonored Contributor
Honored Contributorcheck your mixer is working. Or use one frequency at a time.
After that check that your filter is cutting off as required and with enough stop band attenuation. I also notice that your spectrum is not symmetrical. Are dealing with a complex signal?
