Decimatio FIR filter in FPGA

I have limited the cutoff freq to satisfy the decimation requirements (<=5MHz for 1st, and <=1.25MHz for 2nd). Actually, I let both of them be 1 MHz. Now, I used a mixer before the decimation FIR filters. The input to the filters include two frequencies; i.e.,fi+fc and fi-fc, where fc is the center frequency of the tuner and fi is the input frequency. I'd like to have the fi-fc and remove fi+fc, but the result still wraps up. I'm very confused about this.

The attached figure is the spectrum of the output from the 1st filter. In this experiment, the input frequency is 25.58MHz, and the tuning center frequency is 24.98MHz. We can the desired frequency 0.6MHz, but we can also see the spurious signal -0.56MHz which is the wrapped up from the signal of -50.56MHz.

Thanks a lot for any comments and help!