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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Good point.

The first filter samples at 120Mhz but outputs at 10MHz, hence must cutoff at 5Mhz.

The second filter samples at 10 MHz and outputs at 2.5MHz, hence must cut off at 1.25MHz

any cut off below that is only correct if your signal doesn't include that range of frequency otherwise you cut your signal off.

make sure the cutoff is entered correctly: for 1st filter = 5/120

for 2nd filter = 1.25/10