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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
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Altera_Forum
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15 years ago

Thanks, kaz. You mean the least cutoff freq should be no less than 1.25 MHz. If I would like to have the cutoff freq to be 1 MHz, then I should have another single rate FIR filter in the following. Is that right?

Does the requirement for cutoff freq also suit for the 1st decimation fir? I mean the cutoff freq for the 1st decimation FIR should also be no less than 1.25 MHz?