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Altera_Forum
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15 years ago

Decimatio FIR filter in FPGA

Hi, I was required to build a decimation filter using FIR filter (CIC filter cannot be used). I used FIR compiler to implement the decimation filter. The sampling frequency of ADC is 120 MHz, and I n...
Altera_Forum's avatar
Altera_Forum
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15 years ago

assuming the cutoff is adequate then a possible area to cause spur is overflow of output data in your filter leading to wrapping up of results.

your cutoff must be at least 0.5*1/48 of 120MHz = 1.25MHz