Debugging PCIe DMA transfer example design

Thank you Ven ting.

I was trying to create a signal tap instance with nodes at signals *avalon_streaming source data* (data from data generator to FIFO and related valid and ready signals), *fifo_read_outdata* (data out from the FIFO to the emif interface DDR4) and signals of ctrl_amm_0. But somehow the data wave form is not getting in the Signal Tap GUI Data tab. The clock I used to drive the signal tap is the clock to the datagenerator (CLKUSER_100). Anything I am missing? Also great if you could re-creat it to see anything missing? I am attaching the stp file and a screenshot and a video

I believe the data from FIFO goes to the EMIF through signals of ctrl_amm_0. But I could not locate the data signal (some number of bit width ) in ctrl_amm_0. It would be great if you could point me that.

Also, it would be great if you could look into the modified DMA transfer design file that once I sent to you (through google drive) and verify the connection I made in platform designer is reasonable (for sending the data from FIFO to the DDR4 memory element and then reading that data from host computer through DMA transfer through PCIe)

Hi @Sijith,

From the DESIGN_ST_test.mp4, it seems that the data_generator_avalon_streaming_source_data[31..0] consistently displaying 00000000h which indicates that it is not generating source data as a counter, as you previously described. Consequently, it is expected to observe that no data is stored in the avalon_fifo..

I think you would need to check the data_generator and ensure it can generate data as a counter and store in the avalon_fifo successfully first.

Thanks.

Best Regards,

VenTingT

Hi @Sijith,

Do you have any updates on this?

Thanks.

Best Regards,

VenTingT

Hi VenTing,

I am still working on it and could not resolve the issue you mentioned in the last message. I hope I can resolve it in a couple of days and will update you.. In the meantime, could you please have a look into the modified DMA transfer design (the .qsys file I sent you sometimes before) to see the signal connections I made are good.

Regards

Sijith

Hi @Sijith,

Thanks for letting me know.

From the .qsys file, the signal connections for PCIe part seem good to me.

Thanks.

Best Regards,

VenTingT

Hi @Sijith,

Hope you're doing well.

Do you have further questions on this thread?

Thanks.

Best Regards,

VenTingT

Hi @Sijith,

We have not received any response from you on the previous reply that we provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

VenTingT

Hi @Sijith,

Could you please share your follow-up questions here?

Thanks.

Best Regards,

VenTingT

Hi @Sijith,

Good day.

Could you please drop your follow-up questions in this thread?

Thanks.

Best Regards,

VenTingT

Hi VenTing,

First of all I think, the problem when hooking the Signal Tap up with data generator+ FIFO + DMA example design (modified DMA design) is I could see the data though the output data interface of the data generator + FIFO unit .

1) In this case (when data generator + FIFO) used as an isolated unit and add Signal Tap to it, I have been enforcing avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1 using the button in the FPGA board.

2) But When we add this su-bunit (data generator + FIFO) with DMA example design (to form modified DMA transfer design), we could not see the data_generator_avalon_streaming_source_data[31..0] consistently displaying 00000000h. Here the avalonmm_read_slave_address and avalonmm_read_slave_read connected to the DMA design (not enforcing any values). As I am using same data-generator in case-1 and 2, I suspect its something to do with the state of avalonmm_read_slave_address and avalonmm_read_slave_read. I would like to know what we can do here? Let me know if you need any more information.

Thank you

Regards

Sijith E