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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Debugging PCIe DMA transfer example design

Hi, I would like to have your continued support on this thread. Unfortunately this ticket got closed https://community.intel.com/t5/FPGA-Intellectual-Property/A-design-based-on-the-PCIe-DMA-transfe...
Pcie
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @Sijith,


From the DESIGN_ST_test.mp4, it seems that the data_generator_avalon_streaming_source_data[31..0] consistently displaying 00000000h which indicates that it is not generating source data as a counter, as you previously described. Consequently, it is expected to observe that no data is stored in the avalon_fifo..

I think you would need to check the data_generator and ensure it can generate data as a counter and store in the avalon_fifo successfully first.


Thanks.

Best Regards,

VenTingT