Debugging PCIe DMA transfer example design

Hi @Sijith,

Thanks for attaching the screenshots.

I was able to replicate the error after adding the stp to the design. I believe the error is due to the incorrect nodes added to the stp.

The 'ctrl_amm_0' suggested is an Avalon Memory Mapped Slave. User can capture its signals using Signal Tap. Additionally, its signal nodes are in the signals watching list to monitor using the Signal Tap Analyzer.

For reference, you may check out the signals recommended to monitor in EMIF with the Signal Tap Analyzer in Section 14.4.1 of EMIF Arria 10 FPGA IP User Guide. My apology as EMIF IP is not my area of expertise. Should you have additional questions regarding the EMIF IP, kindly initiate a new forum post for specialized assistance.

Regarding the Capture_stp_send.png, yes, it is normal when you see some of the nodes found to be 'unassigned'. The nodes that were assigned with a specific pin location means they are input/output in the top-level module, and you had assigned them with a specific pin location in the Pin Planner (Assignments > Pin Planner). Alternatively, you may open the .qsf to view the pin assignments.

External Memory Interfaces Arria® 10 FPGA IP User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/signals-to-monitor-with-the-ii-logic.html

You may try to add the Avalon Streaming Source and Sink, and Avalon MM Master and Slave signals that from the IPs that you are targeting to the stp.

Thanks.

Best Regards,

VenTingT