Debugging PCIe DMA transfer example design

Thank you Ven Ting,

I really would like to have your support to complete this project successfully.

1)In the sub-design (Counter_FIFO_SignalTap.zip), I have been setting avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1 using the button in the FPGA board.

2)"Can you the add clock signal that drives the source_data and fifo_o_out_readdata, and the signals that carry the data before passing it to the fifo_o_out_readdata signal in the Signal Tap to check that the correct data are passed to fifo_o_out_readdata?"

You mean I have to add th clock signal that drives the source_data and fifo_o_out_readdatain the SignalTap GUI window to view it? Then The signalTap should run in some different clock? I mean the default clock? (currently signal tap is running in the same clock as clock signal that drives the source_data and fifo_o_out_readdata .

3) "did you compile successfully on the original PCIe DMA transfer example design without adding Signal Tap?"

Yes I did

4)"There is a similar issue discussed in the Intel Community Forum."

In the thread you mentioned basically talks about compilation problem related to adding an IP to a design (so he can change it easily). Unfortunately I could not reach to a conclusion from that thread. But in this case I gets error when I add signal tap instance and at nodes that where the design connects to DDR4 pins (I believe I did it correctly), the error "Error(17046): Illegal connection found on I/O output buffer primitive u0|emif_ddr4_b|emif_ddr4_b|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b|cal_oct.obuf to DDR4B_A[1]. The IO output buffer should only drive out to a top-level pin" happens when try to signal Tap at the node `DDR4B_A[1]`. I dont know why it is illegal to do so in this case?
(Screenshot of selected nodes are attached) FYI: My intention was to see the data flow (that created in the data generator and then streaming through avlonFIFO) to the DDR4

Regards,

Siji