Occasional ContributorDebugging failed DMA
Hello Everyone
I am using Agilex7 FPGA. I am using Multi Channel DMA FPGA IP for PCI Express - Data movers only Example design and have modified example design to fit into my needs.
BAR0 is 16KB - In lspci I can sees that BAR 0 starting offset is 9600_0000h
Internally I have a AVMM FIFO, its write port (512 bits - 64bytes) is connected po_h2ddm_master port with address mapping of 40h to 7fh
For initial testing I want to move 64 byte from host side memory to device internal FIFO .
so, I am choosing My src_addr as 9600_0000h and dest_Addr as 40h.
From Signal Tap analysis I can see that my custom RTL is sending h2d descriptor as per description in link below.
H2D descriptor I sent is as following
[255:192] - 0000_0000_0000_0000h
[191:128] - 0020_8000_0000_0040h
[127: 64] - 0000_0000_0000_0040h
[63 : 0] - 0000_0000_9600_2000h
The response I am getting h2ddm-desc-status interface tell me that DMA has failed as bit 19 is set to '1'. H2D_Desc_status I am getting is 0008_0000h.
I need help debugging failed DMA. I can reproduce this easily. The documentation says "CISE to elaborate on error condition". What does CISE mean? how do I get more details on Why DMA is failing ?
I resolved this issue by writing my custom driver function from example driver provided by altera. The bottom line was offset 9600_0000h is mapped to PCIe device bar space and my original assumption was since its a physical address , this offset can work. But it was failing.
So I reviewed and used the same driver function as in example code base to allocate huge pages. Ot top I added my enhancements to initialize values I wanted and now this DMA is passing; from application side I can also see content of huge page getting updated.
