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UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Debugging failed DMA

Hello Everyone I am using Agilex7 FPGA. I am using Multi Channel DMA FPGA IP for PCI Express - Data movers only Example design and have modified example design to fit into my needs. BAR0 is 16KB -...
  • UserID4331231's avatar
    UserID4331231
    11 months ago

    I resolved this issue by writing my custom driver function from example driver provided by altera. The bottom line was offset 9600_0000h is mapped to PCIe device bar space and my original assumption was since its a physical address , this offset can work. But it was failing.

    So I reviewed and used the same driver function as in example code base to allocate huge pages. Ot top I added my enhancements to initialize values I wanted and now this DMA is passing; from application side I can also see content of huge page getting updated.

UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

there is typo above and I cant edit the post so adding fix here. "so, I am choosing My src_addr as 9600_2000h and dest_Addr as 40h."

Also the reason I am using 9600_2000h address as this address is mapped to BAR0 and I have preloaded BAR 0 with known patterns. So my intention is to use DMA to read some data from BAR0 memory to internal FIFO. And next step is to read FIFO internally and confirm the pattern.