DE0-CV - SDRAM Controller IP Core

Dear Nassos,

Regarding the SDRAM controller IP, yes you may follow the user guide in provided link above. Also, here is another user guide which included DDR3 SDRAM controller (with UNIPHY) as well --> https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf

Feel free to check out this EMIF homepage which centralizes all the information you need to create a memory interface: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-external-memory-interface.html

I can see that you wanted a controller that have Wishbone interface. To be frank, I am not really familiar with this Wishbone interface. Anyway, I did some internal searching and found this page and hope this is helpful --> https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/eureka-technology-inc-/ip/ahb-to-sdram-controller.html?wapkw=sdram

Let me know if you have any concern.

Thanks

Regards,

Aida

UP

Is anyone monitoring these discussions?

Hi,

some more information in case someone is interested in helping me.

I want the SDRAM Controller to have a WishBone interface.

To my knowledge, from the searching I have done up to this point, Intel doesn't seem to provide a controller compatible with Wishbone bus.

Is this really the case?

I would really appreciate it if anyone from the Intel Support team or the rest of the Forum's members could give me an answer on this matter.

It is very important for the project I am trying to implement.

Thank you in advance for your responses!

Kind regards,

anm

Dear @anm​ ,

Please allow me sometime to look into your issue and I will update to you ASAP.

Thanks

Regards,

Aida

Hi Aida,

thank you very much for your interest and your time.

I will be awaiting your response on this.

Kind regards,

Nassos

Dear Aida,

thank you very much for your quick response, I will check on the content you send me on the first 2 links and I will get back to you soon.

One question regarding the 3rd link:

I stumbled upon this IP from "Eureka Technology Inc." too. Is this included as an IP in Quartus? Or is it a paid license IP and I need to contact Eureka for it?

Kind regards,

Nassos

Dear Aida,

those 2 links do not include Cyclone V in their supported devices:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ddr_sdram.pdf

https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf

Do you think that might be problem for me? To be honest I searched through the Intel's db and I wasn't able to track a User Guide for Memory Controllers suitable for Cyclone V.

So my guess is that the above might be suitable for Cyclone V too. Can you verify it?

Some more info, this is the data-sheet of the external memory of the DE0-CV board: http://www.issi.com/WW/pdf/42-45R-S_86400F-16320F.pdf

The interface ports of the memory are the following:

Kind regards,

Nassos

Hi Nassos,

Please allow me to address your questions as below:

Q1) I stumbled upon this IP from "Eureka Technology Inc." too. Is this included as an IP in Quartus? Or is it a paid license IP and I need to contact Eureka for it?

[Aida]: I am not really sure about this IP as I’m not familiar with it. It the website, it mentioned “For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com”, so I guess yes you should contact Eureka for more details.

Q2) those 2 links do not include Cyclone V in their supported devices:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ddr_sdram.pdf

https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf

Do you think that might be problem for me? To be honest I searched through the Intel's db and I wasn't able to track a User Guide for Memory Controllers suitable for Cyclone V.

So my guess is that the above might be suitable for Cyclone V too. Can you verify it?

[Aida]: The Cyclone V device family supports both hard and soft interfaces for DDR3, DDR2, and LPDDR2 SDRAM memory protocols. You refer to Chapter 6: External Memory Interfaces in Cyclone V Devices of this Cyclone V handbook.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

The two documents attached previously are the old version which is during Altera time (now part of Intel) thus it might not be updated with latest devices. But you may refer to the Cyclone V handbook which mentioned on the supported EMIF IP as I explained above. You can generate the design and assigned the pin placement as the interface port of the memory. For latest version (Intel version), you may download the EMIF handbook which centralized all the information regarding EMIF IP on how to get started, design guidelines and also reference materials in the link I shared previously --> https://www.intel.com/content/www/us/en/programmable/support/literature/lit-external-memory-interface.html

Thanks

Regards,

Aida