Forum Discussion

anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

DDR4 EMIF IP Inquiry for Arria 10

Dear A10 DDR4 EMIF IP Owners, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect th...
Memory
anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

Sorry for the late reply. Do you mean that I should change pll_ref_clk and oct_rzqin's pin constraints so that they need to be in IO Bank 2K for HPS and 3B for FPGA instead of 2J and 3A respectively ?

I'm attaching my current constraints (converted to txt) for HPS and FPGA here. Looking forward to your response.

Kind regards

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi @anonimcs

    According to the ddr4.txt, IO Bank 2K for HPS and IO Bank 3B for FPGA are the Address and Command group.

    You should place the pll_ref_clk and oct pins in that IO Bank.

    Regards,

    Adzim