Contributor
Regular ContributorHi
The pin location for pll_ref_clk and oct_rzqin signals are not following the recommended location provided in the Arria 10 EMIF User Guide. Link: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/general-guidelines-39744-01.html
Please place both pins in Address & Command group as it will affect the timing result.
If the timing violation still occur, you may need to reconstruct the pin location of the design or optimize the timing by reconfiguring the Synthesis and Fitter setting.
The link below shows some settings that might assist you in resolving core timing issue, but you may use your previous setting as well to resolve the issue.
Link: https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/optimizing-timing.html
Regards,
Adzim
ContributorSorry for the late reply. Do you mean that I should change pll_ref_clk and oct_rzqin's pin constraints so that they need to be in IO Bank 2K for HPS and 3B for FPGA instead of 2J and 3A respectively ?
I'm attaching my current constraints (converted to txt) for HPS and FPGA here. Looking forward to your response.
Kind regards
Contributor@AdzimZM_Intel @WeiHanT_Intel any comments ?
Regular ContributorHi @anonimcs
According to the ddr4.txt, IO Bank 2K for HPS and IO Bank 3B for FPGA are the Address and Command group.
You should place the pll_ref_clk and oct pins in that IO Bank.
Regards,
Adzim
