Contributor
Regular ContributorHi
Based on the DDR timing report, the timing violation occurred in Core path.
Usually this timing violation is not inside the EMIF IP module, but it is within the EMIF IP module and other module in your design.
You may check the clock supply to the other module in this case.
The EMIF IP may need the user logic connected to it, to run at quarter rate of memory clock frequency.
You can change the clock supply to has a quarter rate frequency supplied to the user logic.
Regards,
Adzim
ContributorHi,
I believe you mean this clock "fpga_emif_ddr4_core_usr_clk" in fpga_emif_ddr4 module. For this design, it's indeed less than a one fourth of the memory's clock, but I also have another design (with same modules, only with different generic values) where the fpga_emif_ddr4_core_usr_clk is exactly one fourth of the memory clock. But even in that design, I got similar timing violations (the place of the violation is the same, the negative slack is close to what I shared before). So I don't think the frequency of fpga_emif_ddr4_core_usr_clk is my issue here...
