New Contributor
Super ContributorIf this is Avalon, waitrequest is active high, not active low, so you have to hold the address and read control until waitrequest goes low. One cycle after waitrequest goes low is when valid data appears, qualified, in the case of a burst, with readdatavalid.
See the Avalon spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html
New ContributorContinuing from my previous reply, I'd say this part is not correct
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One cycle after waitrequest goes low is when valid data appears, qualified, in the case of a burst, with readdatavalid
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From Figure 15, paragraph 3 in chapter 3.5.5.2. Read Bursts
"Host B drives address (A1), burstcount, and read. The agent asserts waitrequest, causing all inputs except beginbursttransfer to be held
constant. The agent could have returned read data from the first read request at this time, at the earliest."
Implying that the agent may delay the readvalid response, which makes sense. For an emif IP that must fetch data from outside the fpga, one must expect several cycles of delay
