DDR2 Troubles on Cyclone III

I'm having some trouble with DDR2 interface on a Cyclone III system. I'm using v. 9.1 of the tools, SOPC builder with the Legacy High Performance Full Speed Controller, 133MHz memory clock. The memory modules are 2ea 16bit wide MT47H16M16-3 chips, each with a dedicated clock.

If I write a pattern such as this:

Address Base+0 - 0x11111111

Address Base+4 - 0x22222222

Address Base+8 - 0x33333333

Address Base+C - 0x44444444

The read back will be this:

Address Base+0 - 0x33113311

Address Base+4 - 0x44224422

Address Base+8 - 0xXX33XX33

Address Base+C - 0xXX44XX44

This looks to me as if the lower bytes access correctly while the upper bytes are off a clock. I don't know if the issue is on a read or write or both - any ideas on how to check if the issue is read or write would be helpful.

My design meets timing.

I'm not a DDR2 expert, but I've verified the the DDR2 core presets against the datasheet, and have used identical preset file successfully on Aria designs.

Does anyone have experience with similar issues or ideas on solutions?