DDR2 timing problem on arbiter

You are most probably right about the failing path not directly linked to the DDR2. It hops around.

The problem is that the whole system is synchronous to the DDR2's PLL either with auxhalf or sysclk (auxhalf being the avalon's clock which is not connected to the DDR2 data bus and sysclk which are sent to the two modules connected to the DDR2 data bus). Thus the PLL used is the DDR's.

Any clues as how I can figure out what is the cause? I have to admit that I'm a Xilinx guy in an Altera world. Seeing clock skew in fabric from clock to same clock is a weird concept. The purpose of a clock tree is to eliminate (or minimize for the real world) the skew.

Maybe you can explain what I see in TimeQuest.

I get:

Slack: -5.009 (understood)

From Node: soc:soc0|ddr2_sdram_s1_arbitrator:the_ddr2_sdram_s1|ddr2_sdram_s1_slavearbiterlockenable

To Node: soc:soc0|ddr2_sdram_s1_arbitrator:the_ddr2_sdram_s1|ddr2_sdram_s1_slavearbiterlockenable (so far so good)

Launch Clock: soc0|the_ddr2_sdram|ddr2_sdram_controller_phy_inst|ddr2_sdram_phy_inst|ddr2_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]

Latch Clock: soc0|the_ddr2_sdram|ddr2_sdram_controller_phy_inst|ddr2_sdram_phy_inst|ddr2_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] (easy enough)

Relationship: 8.000 (multicycle path??? Period??? This clock is 125MHz)

Clock Skew: -0.537 (not bad; could be better)

Data Delay: 12.470 (this wire either has a whole lot of destination or it's doing the milk man's run)

How can I figure out what is the cause of this?

I am not good at timing settings... Sorry.

Small question: which exact version of Quartus do You use?

I'm not bad at timing for Xilinx, Altera is still weird to me. I only need to grasp what the whole picture means....

I am using the latest Quartus 11.1.

this is the issue Socrates was referring to. 11.1sp1 includes the fix

http://www.altera.com/support/kdb/solutions/rd11182011_10.html