Forum Discussion

Honored Contributor

14 years ago

DDR2 timing problem on arbiter

Hi, I've been having a problem on the avalon arbiter regarding DDR2. The signal "slavearbiterlockenable: is giving me between 10 and 15 ns of setup violation. I have two masters conne...

Altera_Forum

Honored Contributor

14 years ago

this is the issue Socrates was referring to. 11.1sp1 includes the fix

http://www.altera.com/support/kdb/solutions/rd11182011_10.html

Forum Discussion

DDR2 timing problem on arbiter

Recent Discussions

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models