DDR2 SODIMM Verification + probing solutions

I'm not understanding. Is you're board fabricated and not working or are you designing a board now?

Jake

I'm designing now - but for validation of protocol, timings etc on real hardware I want to use our logic analyser - to do this I need to make a physical connection between the logic analyser probes and the DDR2 SODIMM. See NexusTechnology products at www.busboards.com/ (http://www.busboards.com/)

I wondered if anyone on this forus has any experience of using either an Interposer or a Nex-Vue product?

Stephen

Okay well I'm not going to claim to be an authority on this. At one time I worked for a very large DRAM manufacturer. I designed Flash, DDR, and DDR2 memory test equipment.

First you need to ask yourself what it is you are trying to analyze.

1 - Are you designing your own memory controller and need to analyze gross timing of your control / data signals? A logic analyzer is appropriate and useful in this case and I wouldn't hesitate suggesting that you buy the interposer.

2 - Are you just anticipating problems in your PCB layout and want to be able to analyze them when the memory doesn't work? A logic analyzer is not as useful here. It may help tell you if you've got an open or short somewhere. It might reveal if you've made some dramatic mistake (like making one DQ trace in a group far too long or short compared to the others). But if you are trying to view the signal integrity of the signals, this is not going to help.

. If you measure the signals anywhere except at the destination pins (FPGA or memory pins depending on who's driving), the signal is not going to look good. I'm sure you understand why this is the case.

If you need to do some signal integrity checking, it's best to probe the module at the via that connects to the ball in question. We would often take a DIMM or SODIMM and rip some of the parts off it so we could probe at the best places. Or we would solder little test pins to the module so we could connect an oscope or logic analyzer to them.

Again, just my opinion. Maybe somebody else will have something better.

Jake

Thanks Jake.

Just to put things in context - this is our very first DDR2 design, we want to ensure that the IP controller is working OK, that we'ce configured it properly, that the DDR2 is initialised Ok and mode registers loaded with correct data, we're not violating the protocol regarding timings between issuing commands, refreshes etc.

I know for SI work I'll need to get the scope and active probes out but for the type of stuff described the analyser is a good tool. I don't want to blow our budget on an interposer which probes at the SODIMM fingers where SI is not great (Nexus don't guarentee that the analyser will be able to capture properly here) whereas the Nex-Vu product probes at the DRAMM balls wher e our simulations show acceptable SI.

Our design will be populated with two different densities of SODIMM so ideally I want to verify both modules - one interposer would do the job but it would take two Nex-Vue boards (at many $)

Stephen

Are you using the Altera DDR2 controller?

Jake

Yes Jake - the HP Memory Controller.

Stephen

I would say rest assured the Altera HP memory controller works. I have complete confidence in it as I've used it in several Stratix II designs now. Altera's memory controllers are really very good and very easy to use.

The best thing you can do is what you're already doing:

1 - Simulate using Hyperlynx. This is priceless and it's great that you've had access to the tool to do it.

2 - Constrain, constrain, constrain the interface on the PCB. Even if you spend an extra 3 days in layout doing trace matching it's worth it. Follow the guidelines provided by the memory manufacturers (primarily Micron). Don't hesitate to overconstrain a bit.

If you are going to have any problems with your memory interface it will be:

1 - A poor layout.

2 - A schematic mistake (didn't connect something properly).

My most recent board has two DDR2 SODIMMs on it. My current company does not have the luxury of Hyperlynx. We don't even have a logic analyzer and there is not a scope in this entire building with an active probe that can measure DDR2 signals. All we could do is follow the rules. Both of those DIMMS fired up first time at 333MHz (limit for Stratix II) with the HP controller and ran without a single issue. So far I've never even had to look at the signals. Follow good PCB design rules and you should be just fine.

Jake

Thanks again Jake.

Regarding HyperLynx - we didn't budget for this initially - but you can hire it by the month which we did and it was very worthwhile. Check out your Mentor rep if the offer that where you are.

The main issue in layout we're facing is trying to distribute the power nets around the FPGA which ends up splitting planes. We're striving not to have any high-speed DDR2 nets crossing over any of these splits as per memory and FPGA vendor's app. notes. Any feedback on this particular issue would be good.

Stephen