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Altera_Forum's avatar
Altera_Forum
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14 years ago

DDR2 memory controller implementation ...

Hey guys,

I am a newbie to Quartus and I am doing a project on the DE4 board wherein I need to store lots of values in the external memory. So i have been looking into the DDR2 memory controller implementation. What i found out that the IP core for the controller is generally used with the NIOS II soft processor for implementation. However this makes the memory operations slow. Thus, I was trying to get ONLY the sole controller core running without using NIOSII.

Can you guys please let me know, if this is possible to do??

The whole point is that I just need to perform simple write and reads from the DDR2 memory and don't wanna use the soft processor!

I would really appreciate your help!

Thanks & Regards,

-Murtaza:)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, it is possible to use HPC or HPC II without NIOS. You will just need to add a small state machine to feed that data in and out of the interface. If you are reading and writing to the DDR at the same time, your state machine will get a little complex. However, if you write data, then read it, the state machine is a lot simpler. Download the doc of HPC and look at it. It is not too hard to understand. Unfortunately, most of the documentation out there is related to NIOS/DDR usage.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Remember:

    1, Always obey write_data_request. (that is the one telling you that the ddr2 is ready to accept data, do all your counts on this)

    2, Use the ddr2 auk clocks for your state machine.

    3, Use dual clock fifos if you need to burst things.

    4, Half rate interface is the easiest one to deal with timing wise.

    Probably more things but that is generally it. It only requires a small state machine to work, we have done 4 designs with dual 2x128MB DDR2, and it works fine.

    Never done any eval boards, though.

    apus