DDR2 memory controller implementation ...

Remember:

1, Always obey write_data_request. (that is the one telling you that the ddr2 is ready to accept data, do all your counts on this)

2, Use the ddr2 auk clocks for your state machine.

3, Use dual clock fifos if you need to burst things.

4, Half rate interface is the easiest one to deal with timing wise.

Probably more things but that is generally it. It only requires a small state machine to work, we have done 4 designs with dual 2x128MB DDR2, and it works fine.

Never done any eval boards, though.

apus