DDR2 IP Controller Write Performance Question

Are you talking about the Altera DDR2 controller? I don't think your assumption is valid that the controller will queue up 4 single-word writes on the host side, recognize that the word addresses are consecutive, then generate one 4-word burst to the memory. I think it will generate a separate burst write to memory in reponse to each single-word write. So one 4-word burst on the host side will be way more efficient than 4 single-word writes. At least 4x faster I would think. You should try both approaches and see what you get.

The controller itself is pretty efficient on the host interface. How effecient is partly under your control in how you interact with it. There's a lot more overhead on the memory side, especially for short bursts. The longer your bursts are on the host side, the more efficient the interactions with the memory will be. You can configure the controller to allow bursts up to 64 words on the host side (in my case anyway for a 128-bit wide full-rate DDR2 controller). This is the "Local Maximum Burst Count" setting on the "Controller Settings" tab in the MegaWizard. We stream data from a high-speed image sensor to DDR2 memory (pair of SODIMMs) and I use the maximum burst size allowed whenever possible (1k bytes per burst on the host side). When doing this we achieve > 90% of the theoretical write bandwidth of the memory (2*mem_width*mem_clk_frequency). Short bursts, interleaving writes and reads, jumping aorund to different banks, etc, will all hurt your throughput.

Thanks for the valuable feedback. Unfortunately, the burst size is limited to 4 per the board vendor (Opal-Kelly ZEM4310 board with a Cyclone IV E). I'm not sure where this constraint comes from, the on-board SDRAM (16-bit IO) or the Altera DDR2 controller, or a combination. The Altera documentation says 4 in places, 8 in other places, and up to 64 in yet others, depending on the context. A larger burst size sure would be helpful.