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Are you talking about the Altera DDR2 controller? I don't think your assumption is valid that the controller will queue up 4 single-word writes on the host side, recognize that the word addresses are consecutive, then generate one 4-word burst to the memory. I think it will generate a separate burst write to memory in response to each single-word write. So one 4-word burst on the host side will be way more efficient than 4 single-word writes. At least 4x faster I would think. You should try both approaches and see what you get.
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Yes, it's the Altera DDR2 full-rate controller running at 133MHz.
I assume burst writes are there for a reason, so I guess I'm asking if someone can explain where the improvement comes from and how much. Assuming the controller won't create an SDRAM burst write command from multiple single requests, I can see where one SDRAM command with 4 data words (2 clocks for data transfer) would be faster. Does anyone know what the Altera DDR2 controller will or will not do for writes in terms if efficiency?
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