DDR2 IP Controller Write Performance Question

The controller itself is pretty efficient on the host interface. How effecient is partly under your control in how you interact with it. There's a lot more overhead on the memory side, especially for short bursts. The longer your bursts are on the host side, the more efficient the interactions with the memory will be. You can configure the controller to allow bursts up to 64 words on the host side (in my case anyway for a 128-bit wide full-rate DDR2 controller). This is the "Local Maximum Burst Count" setting on the "Controller Settings" tab in the MegaWizard. We stream data from a high-speed image sensor to DDR2 memory (pair of SODIMMs) and I use the maximum burst size allowed whenever possible (1k bytes per burst on the host side). When doing this we achieve > 90% of the theoretical write bandwidth of the memory (2*mem_width*mem_clk_frequency). Short bursts, interleaving writes and reads, jumping aorund to different banks, etc, will all hurt your throughput.