DDR2 IP Controller Write Performance Question

Are you talking about the Altera DDR2 controller? I don't think your assumption is valid that the controller will queue up 4 single-word writes on the host side, recognize that the word addresses are consecutive, then generate one 4-word burst to the memory. I think it will generate a separate burst write to memory in reponse to each single-word write. So one 4-word burst on the host side will be way more efficient than 4 single-word writes. At least 4x faster I would think. You should try both approaches and see what you get.