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Honored ContributorDDR2 HP simulation fail in StratixIV
hi all,
I want to simulate DDR2 HP ip core. I use the altera example as top file. According to altera docment, I do the following: 1. I download simulation model from Micron and add `define sg37E `define x8 and `include "ddr2_parameters.vh" to simulation model 2. create DDR2 HP core and generate simulation model 3. modify tb file. replace altera mem_model with Micron model 4. compile the library vlib altera_library# basic libraries vlib altera_library/lpm vmap lpm altera_library/lpm vcom -93 -work lpm {d:/tools/quartus9.1/quartus/eda/sim_lib/220pack.vhd} vcom -93 -work lpm {d:/tools/quartus9.1/quartus/eda/sim_lib/220model.vhd} vlib altera_library/altera vmap altera altera_library/altera vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_primitives_components.vhd} vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_primitives.vhd} vcom -93 -work altera {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_syn_attributes.vhd} vcom -93 -work altera {d:/tools/quartus9.1/quartus/libraries/vhdl/altera/altera_europa_support_lib.vhd} vlib altera_library/altera_mf vmap altera_mf altera_library/altera_mf vcom -93 -work altera_mf {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_mf_components.vhd} vcom -93 -work altera_mf {d:/tools/quartus9.1/quartus/eda/sim_lib/altera_mf.vhd} vlib altera_library/sgate vmap sgate altera_library/sgate vcom -93 -work sgate {d:/tools/quartus9.1/quartus/eda/sim_lib/sgate_pack.vhd} vcom -93 -work sgate {d:/tools/quartus9.1/quartus/eda/sim_lib/sgate.vhd}# component dependent libraries# ALTGXB vlib altera_library/ALTGXB vmap ALTGXB altera_library/ALTGXB vcom -93 -work ALTGXB {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd} vcom -93 -work ALTGXB {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd}# stratixiv vlib altera_library/stratixiv vmap stratixiv altera_library/stratixiv vcom -93 -work stratixiv {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_atoms.vhd} vcom -93 -work stratixiv {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiv_components.vhd}# stratixiii vlib altera_library/stratixiii vmap stratixiii altera_library/stratixiii vcom -93 -work stratixiii {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiii_atoms.vhd} vcom -93 -work stratixiii {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixiii_components.vhd}# stratixgx vlib altera_library/stratixgx vmap stratixgx altera_library/stratixgx vcom -93 -work stratixgx {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixgx_mf.vhd} vcom -93 -work stratixgx {d:/tools/quartus9.1/quartus/eda/sim_lib/stratixgx_mf_components.vhd} 5. compile the HDL file, the step is ok. vlib work vmap work work vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_pll.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_seq_wrapper.vho} vcom -93 -work work {d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho} vcom -93 -work work {d:/ddr-s/sim/ddr2_phy.vho} vcom -93 -work work {d:/ddr-s/sim/ddr2.vhd} vlog -work work {d:/ddr-s/sim/ddr2_micron.v} vcom -93 -work work {d:/ddr-s/sim/ddr2_example_top.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_controller_phy.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_pll.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_phy_alt_mem_phy_seq.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_example_driver.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_ex_lfsr8.vhd} vcom -93 -work work {d:/ddr-s/sim/ddr2_example_top_tb.vhd} 6. then I do simulation, but I fail. I don't know the reason. vsim -t ps -novopt work.ddr2_example_top_tb Please help me check if I miss any HDL file。 I attached the error information in the attachment file. thank you very much. Tom
