DDR2 HP simulation fail in StratixIV

hi all,

the error picture size is too big, so I copy it here.# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'cs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'cke' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'ck_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_controller_phy.vhd(384): No default binding for component at 'ddr2_auk_ddr_hp_controller_wrapper_inst'.# (Port 'ck' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'odt' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dqs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dqs' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dq' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'addr' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ba' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'dm_rdqs' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'we_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cas_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ras_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cs_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'cke' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ck_n' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Error: (vsim-3732) d:/ddr-s/sim/ddr2_auk_ddr_hp_controller_wrapper.vho(16150): No default binding for component at 'niol1li'.# (Port 'ck' is not on the entity.)# Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_auk_ddr_hp_controller_wrapper_inst/niol1li# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_delay_delay_gen_0_postamble_preset_delay_8840 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_delay_delay_gen_1_postamble_preset_delay_8839 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_dqs_ip_dqs_group_0_dqs_ip_ddr2_phy_alt_mem_phy_delay_dqs_enable_delay_8013 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# ** Warning: (vsim-3473) Component instance "ddr2_phy_ddr2_phy_alt_mem_phy_ddr2_phy_alt_mem_phy_inst_ddr2_phy_alt_mem_phy_dp_io_dpio_ddr2_phy_alt_mem_phy_dqs_ip_dqs_group_1_dqs_ip_ddr2_phy_alt_mem_phy_delay_dqs_enable_delay_7047 : ddr2_phy_alt_mem_phy_delay" is not bound.# Time: 0 ps Iteration: 0 Region: /ddr2_example_top_tb/ddr/ddr2_controller_phy_inst/ddr2_phy_inst File: d:/ddr-s/sim/ddr2_phy.vho# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./compile.do PAUSED at line 19

regards

tom