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Honored Contributor
Honored ContributorDDR2 highperformance controller local_init_done, s_tracking_setup deadlock
Dear all, I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, ...
Altera_ForumHonored Contributor
Honored ContributorSome other ideas:
Have you added board trace models to Quartus so that it accurately sets the delay chains? Have you done a board sim to check SI? Have you set the address/command clock phase correctly?
