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Altera_Forum's avatar
Altera_Forum
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15 years ago

DDR2 highperformance controller local_init_done, s_tracking_setup deadlock

Dear all, I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If I understand your problem correctly, the PHY calibration doesn't always pass, thus the low local_init_done signal.

I have some question:

- Is this hardware/simulation?

- If this is hardware, I assume that in one compilation flow, calibration doesn't always pass. Am I correct?

- If yes to above question, this is most probably calibration timing problem. Then you'll have to look at TimeQuest report, does your design pass timing marginally?

Hope that helps.