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Altera_Forum
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15 years ago

DDR2 highperformance controller local_init_done, s_tracking_setup deadlock

Dear all, I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It showed that it must actualy be a timing issue of some sort. A subsequent compilation (I just added some signals in the SignalTap) did not show the behaviour (no deadlock in DDR2 HPC initialisation). I had no timing analyzer warnings in all the versions (i.e. timing closed), and the DDR2 generated .sdc is in place where it should. Any hint in which direction to push?

Regards,

Peter